1. Field of the Invention
The present invention relates to a sign generation system for a carry save adder, and more particularly to a sign generation system suitable to a multiple generation type multiplier which uses a carry save adder.
2. Description of the Prior Art
In a conventional multiple generation type multiplier, a carry save adder is used to sum multiples. The carry save adder can attain a high speed addition with a fewer stages than a carry propagate adder does, but since an output is divided into a sum and a carry, the number of bits of the sum and the carry is larger than the number of bits of a product predicted by the numbers of bits of a multiplier and a multiplicand. For the multiplication of data represented by two's complement, the number of bits of the product is represented by n.ltoreq.l+m-1 where l, m and n are the numbers of bits of the multiplicand, the multiplier and the product with one bit being assigned to a sign bit. The sign of equality is met when both the multiplicand and the multiplier are negative numbers and absolute values thereof are maximum.
As an example, let us consider a multiplication of 1.times.3=3. In this case, the number of bits of the product is predicted to be no larger than four because the number of bits of the multiplicand is two, the number of bit of the multiplier is three and the number of bit of the sign is one. FIG. 1 shows an actual operation process of the above multiplication which is carried out by a CSA tree group comprising two stages of carry save adders (CSA's) 103 and 104. The data inputted to the CSA 103 has six bits including extended sign bits. The multiples "000100" and "111111" representing 2.sup.2 -2.sup.0 =4-1 are generated by a Booth multiple generation method. Through two sums of the CSA addition by the CSA tree group 102, a sum of -13 and a carry of +16 are generated. Therefore the data field requires five bits. Accordingly, the sum and the carry both require six bits, respectively, to represent the results, with one bit being used for the sign.
The final result (+3) of the above multiplication is obtained by inputting the sum and the carry to a carry propagate adder (CPA) 105 as shown in FIG. 1.
If, however, a succeeding operation should be carried out, i.e., if the sum and the carry are to be summed in the next stage carry save adder, the data field having a larger number of bits for a sum and a carry than the number predicted by the numbers of bits of the multiplicand and the multiplier used to calculate the sum and the carry is propagated as it is, but the sign field must be expanded. Many circuits are required to expand the sign field and a circuit delay is included by those circuits.